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These models can be represented at different abstraction levels according to the more or less detailed descriptions of some properties related to communication (channel, protocol, etc). Furthermore, the same models can also be classified according to the way synchronization is achieved in order to carry out communication. In the following section, taxonomies for the most commonly used interconnection execution models are presented. 1 Existing Interconnection Execution Models Several execution models exist to perform interconnections.

FIFO-based communication is an example of this mode. 3 Interconnection Control Abstraction Levels Control is related to behavior (or protocol). This includes scheduling and arbitration functionalities (some resolution functions). Scheduling refers to a set of decisions aimed at establishing an order of application for a set of actions, prior to their execution [Dic05]. Arbitration refers to the process of choosing one of the conflicting demands in order to access a shared resource. Control abstraction levels are established according to the modeling of these functionalities.

When the interconnections are at the physical level, the communication is realized by physical wires and buses. The granularity of the unit time is the clock cycle and the communication primitives are set/reset on ports and waiting a new clock cycle. SystemC [Sys00], Verilog [Moo98], and VHDL [Iee93] are the most used languages to describe systems at this abstraction level. 2 Simulation Interfaces The simulation interfaces enable the communication of the different components of the system through the simulation bus.

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