By David Culler, J. P. Singh, Anoop Gupta
The most enjoyable improvement in parallel laptop structure is the convergence of normally disparate ways on a typical laptop constitution. This e-book explains the forces in the back of this convergence of shared-memory, message-passing, information parallel, and data-driven computing architectures. It then examines the layout concerns which are serious to all parallel structure around the complete variety of recent layout, masking info entry, verbal exchange functionality, coordination of cooperative paintings, and proper implementation of helpful semantics. It not just describes the and software program recommendations for addressing each one of those concerns but additionally explores how those concepts have interaction within the comparable process. interpreting structure from an application-driven point of view, it presents entire discussions of parallel programming for top functionality and of workload-driven assessment, in accordance with realizing hardware-software interactions.
* synthesizes a decade of study and improvement for practising engineers, graduate scholars, and researchers in parallel laptop structure, approach software program, and functions development
* provides in-depth software case experiences from special effects, computational technology and engineering, and knowledge mining to illustrate sound quantitative review of layout trade-offs
* describes the method of programming for functionality, together with either the architecture-independent and architecture-dependent facets, with examples and case-studies
* illustrates bus-based and network-based parallel platforms with case stories of greater than a dozen vital advertisement designs
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Additional resources for Parallel Computer Architecture: A Hardware/Software Approach (The Morgan Kaufmann Series in Computer Architecture and Design)
1 Communication Architecture Given that a parallel computer is “a collection of processing elements that communicate and cooperate to solve large problems fast,” we may reasonably view parallel architecture as the extension of conventional computer architecture to address issues of communication and cooperation among processing elements. In essence, parallel architecture extends the usual concepts of a computer architecture with a communication architecture. Computer architecture has two dis40 DRAFT: Parallel Computer Architecture 9/10/97 Convergence of Parallel Architectures 350 300 319 313 Number of Systems 284 250 200 239 187 198 MPP PVP SMP 150 110 106 100 106 63 50 0 0 11/93 11/94 11/95 73 11/96 Figure 1-12 Type of systems used in 500 fastest computer systems in the world.
A control transfer may have to wait for the depth, or latency, of the processor pipeline, until a particular instruction reaches the end of the pipeline and determines which instruction to execute next. Similarly, instructions which use a value loaded from memory may cause the processor to wait for the latency of a cache miss. Processor designs in the 90s deploy a variety of complex instruction processing mechanisms in an effort to reduce the performance degradation due to latency in “wide-issue” superscalar processors.
Adding processors to the switch is expensive, however, the aggregate bandwidth increases with the number of ports. The cost of adding a processor to the bus is small, but the aggregate bandwidth is fixed. Dividing this fixed bandwidth among the larger number of processors limits the practical scalability of the approach. Fortunately, caches reduce the bandwidth demand of each processor, since many references are satisfied by the cache, rather than by the memory. However, with data replicated in local caches there is a potentially challenging problem of keeping the caches “consistent”, which we will examine in detail later in the book.