By Bruce Jacob, Spencer Ng, David Wang
Is your reminiscence hierarchy preventing your microprocessor from functioning at the excessive point it's going to be? reminiscence structures: Cache, DRAM, Disk exhibits you the way to solve this challenge.
The booklet tells you every little thing you want to learn about the logical layout and operation, actual layout and operation, functionality features and ensuing layout trade-offs, and the strength intake of recent reminiscence hierarchies. You find out how to to take on the demanding optimization difficulties that outcome from the side-effects that could look at any aspect within the complete hierarchy.
As a end result it is possible for you to to layout and emulate the total reminiscence hierarchy.
. comprehend all degrees of the process hierarchy -Xcache, DRAM, and disk.
. review the system-level results of all layout offerings.
. version functionality and effort intake for every part within the reminiscence hierarchy.
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Extra resources for Memory Systems: Cache, DRAM, Disk
For example, at the University of Maryland we use the DRAM section to teach a graduate class called HighSpeed Memory Systems, and we supplement both our general and advanced architecture classes with material from the sections on Caches and Cross-Cutting Issues. The Disk section could support a class focused solely on disks, and it is also possible to create for advanced students a survey class that lightly touches on all the topics in the book. As a reference, this book is targeted toward both academics and professionals alike.
Cost per storage bit/byte/KB/MB/etc. (allows cost comparison between different storage technologies) Die area per storage bit (allows sizeefficiency comparison within same process technology) 10 Memory Systems: Cache, DRAM, Disk In a similar vein, cost is especially informative when combined with performance metrics. The following are variations on the theme: characterize both device fragility and robustness of a proposed solution. ) An important note: cost should incorporate all sources of that cost.
Predictability of access time is another common figure of merit. It is a special aspect of performance that is very important when building real-time systems or systems with highly orchestrated data movement. DRAM is occasionally in a state where it needs to ignore external requests so that it can guarantee the integrity of its stored data (this is called refresh and will be discussed in detail in Part II of the book). Such hiccups in data movement can be disastrous for some applications. 2: An idealized cache lookup.